
module frv_load_queue (
    input clk,    // Clock
    input pd_rst, // 
    input rst_n,  // Asynchronous reset active low

    input                       lsu_req              ,
    input                       lsu_ctrl_unsign      ,
    input                       lsu_ctrl_load        ,
    input                       lsu_ctrl_store       ,
    input                       lsu_ctrl_word        ,
    input                       lsu_ctrl_half        ,
    input                       lsu_ctrl_byte        ,
    input [5:0]     lsu_inst_id          , // Instruction ID
    input                       RAW_flag             ,
    input [32-1:0]              RAW_data             ,
    input                       lsu_flush            ,
    input [5:0]     lsu_flush_id         ,
    input                       lsu_store_ready      ,
    output                      lsu_load_ready       ,
    //LSU Operation Number
    input  [31:0]               lsu_op1_val          ,
    input  [31:0]               lsu_op2_val          ,
    //
    output [5:0]    lsu_resp_inst_id,
    output                      lsu_resp_vld    , 
    output                      lsu_resp_rd_vld , 
    output [5:0]                lsu_resp_rd_ind , 
    output [31:0]               lsu_resp_rd_val , //rd value    
    output                      lsu_exp_vld     , //ignore it when exception feature is not implemented
    //DMem read
    output                      dmem_load_req        ,
    output [5:0]    dmem_load_req_tid    , // request transaction id , ignore it before we implement cache
    output [31:0]               dmem_load_addr       , 
    input  [31:0]               dmem_load_rdata      ,
    input                       dmem_load_ack        ,
    output                      dmem_load_flush      ,
    output [3-1:0]              dmem_load_info       ,
    //DDR read
    output                      ddr_load_req         ,
    output [5:0]    ddr_load_req_tid     , // request transaction id , ignore it before we implement cache
    output [31:0]               ddr_load_addr        ,
    input  [31:0]               ddr_load_rdata       ,
    input                       ddr_load_ack         ,
    input  [5:0]    ddr_load_ack_tid     ,
    //dev read
    // output [5:0]    dev_artid       ,
    output [31:0]               dev_araddr      ,
    // output [2:0]                dev_arprot      ,
    output                      dev_arvalid     ,
    input                       dev_arready     ,
    //rdata ch
    // output [5:0]    dev_rtid        ,
    input  [31:0]               dev_rdata       ,
    input  [1:0]                dev_rresp       ,
    input                       dev_rvalid      ,
    output                      dev_rready      

);
wire lsu_load_req =lsu_req & lsu_ctrl_load & lsu_load_ready & lsu_store_ready;

wire [16-1:0]           entry_req_type_o;
//item out
wire [32-1:0]                    entry_addr_o_0            ;
wire [5:0]           entry_inst_id_o_0         ;
wire                             entry_vld_o_0             ;
wire [4-1:0]                     entry_req_state_o_0       ;
wire [1-1:0]                     entry_req_type_o_0        ;
assign   entry_req_type_o[0] =  entry_req_type_o_0        ;
wire [32-1:0]                    entry_resp_data_o_0       ;
wire [3-1:0]                     entry_req_info_o_0        ;
wire [32-1:0]                    entry_addr_o_1            ;
wire [5:0]           entry_inst_id_o_1         ;
wire                             entry_vld_o_1             ;
wire [4-1:0]                     entry_req_state_o_1       ;
wire [1-1:0]                     entry_req_type_o_1        ;
assign   entry_req_type_o[1] =  entry_req_type_o_1        ;
wire [32-1:0]                    entry_resp_data_o_1       ;
wire [3-1:0]                     entry_req_info_o_1        ;
wire [32-1:0]                    entry_addr_o_2            ;
wire [5:0]           entry_inst_id_o_2         ;
wire                             entry_vld_o_2             ;
wire [4-1:0]                     entry_req_state_o_2       ;
wire [1-1:0]                     entry_req_type_o_2        ;
assign   entry_req_type_o[2] =  entry_req_type_o_2        ;
wire [32-1:0]                    entry_resp_data_o_2       ;
wire [3-1:0]                     entry_req_info_o_2        ;
wire [32-1:0]                    entry_addr_o_3            ;
wire [5:0]           entry_inst_id_o_3         ;
wire                             entry_vld_o_3             ;
wire [4-1:0]                     entry_req_state_o_3       ;
wire [1-1:0]                     entry_req_type_o_3        ;
assign   entry_req_type_o[3] =  entry_req_type_o_3        ;
wire [32-1:0]                    entry_resp_data_o_3       ;
wire [3-1:0]                     entry_req_info_o_3        ;
wire [32-1:0]                    entry_addr_o_4            ;
wire [5:0]           entry_inst_id_o_4         ;
wire                             entry_vld_o_4             ;
wire [4-1:0]                     entry_req_state_o_4       ;
wire [1-1:0]                     entry_req_type_o_4        ;
assign   entry_req_type_o[4] =  entry_req_type_o_4        ;
wire [32-1:0]                    entry_resp_data_o_4       ;
wire [3-1:0]                     entry_req_info_o_4        ;
wire [32-1:0]                    entry_addr_o_5            ;
wire [5:0]           entry_inst_id_o_5         ;
wire                             entry_vld_o_5             ;
wire [4-1:0]                     entry_req_state_o_5       ;
wire [1-1:0]                     entry_req_type_o_5        ;
assign   entry_req_type_o[5] =  entry_req_type_o_5        ;
wire [32-1:0]                    entry_resp_data_o_5       ;
wire [3-1:0]                     entry_req_info_o_5        ;
wire [32-1:0]                    entry_addr_o_6            ;
wire [5:0]           entry_inst_id_o_6         ;
wire                             entry_vld_o_6             ;
wire [4-1:0]                     entry_req_state_o_6       ;
wire [1-1:0]                     entry_req_type_o_6        ;
assign   entry_req_type_o[6] =  entry_req_type_o_6        ;
wire [32-1:0]                    entry_resp_data_o_6       ;
wire [3-1:0]                     entry_req_info_o_6        ;
wire [32-1:0]                    entry_addr_o_7            ;
wire [5:0]           entry_inst_id_o_7         ;
wire                             entry_vld_o_7             ;
wire [4-1:0]                     entry_req_state_o_7       ;
wire [1-1:0]                     entry_req_type_o_7        ;
assign   entry_req_type_o[7] =  entry_req_type_o_7        ;
wire [32-1:0]                    entry_resp_data_o_7       ;
wire [3-1:0]                     entry_req_info_o_7        ;
wire [32-1:0]                    entry_addr_o_8            ;
wire [5:0]           entry_inst_id_o_8         ;
wire                             entry_vld_o_8             ;
wire [4-1:0]                     entry_req_state_o_8       ;
wire [1-1:0]                     entry_req_type_o_8        ;
assign   entry_req_type_o[8] =  entry_req_type_o_8        ;
wire [32-1:0]                    entry_resp_data_o_8       ;
wire [3-1:0]                     entry_req_info_o_8        ;
wire [32-1:0]                    entry_addr_o_9            ;
wire [5:0]           entry_inst_id_o_9         ;
wire                             entry_vld_o_9             ;
wire [4-1:0]                     entry_req_state_o_9       ;
wire [1-1:0]                     entry_req_type_o_9        ;
assign   entry_req_type_o[9] =  entry_req_type_o_9        ;
wire [32-1:0]                    entry_resp_data_o_9       ;
wire [3-1:0]                     entry_req_info_o_9        ;
wire [32-1:0]                    entry_addr_o_10            ;
wire [5:0]           entry_inst_id_o_10         ;
wire                             entry_vld_o_10             ;
wire [4-1:0]                     entry_req_state_o_10       ;
wire [1-1:0]                     entry_req_type_o_10        ;
assign   entry_req_type_o[10] =  entry_req_type_o_10        ;
wire [32-1:0]                    entry_resp_data_o_10       ;
wire [3-1:0]                     entry_req_info_o_10        ;
wire [32-1:0]                    entry_addr_o_11            ;
wire [5:0]           entry_inst_id_o_11         ;
wire                             entry_vld_o_11             ;
wire [4-1:0]                     entry_req_state_o_11       ;
wire [1-1:0]                     entry_req_type_o_11        ;
assign   entry_req_type_o[11] =  entry_req_type_o_11        ;
wire [32-1:0]                    entry_resp_data_o_11       ;
wire [3-1:0]                     entry_req_info_o_11        ;
wire [32-1:0]                    entry_addr_o_12            ;
wire [5:0]           entry_inst_id_o_12         ;
wire                             entry_vld_o_12             ;
wire [4-1:0]                     entry_req_state_o_12       ;
wire [1-1:0]                     entry_req_type_o_12        ;
assign   entry_req_type_o[12] =  entry_req_type_o_12        ;
wire [32-1:0]                    entry_resp_data_o_12       ;
wire [3-1:0]                     entry_req_info_o_12        ;
wire [32-1:0]                    entry_addr_o_13            ;
wire [5:0]           entry_inst_id_o_13         ;
wire                             entry_vld_o_13             ;
wire [4-1:0]                     entry_req_state_o_13       ;
wire [1-1:0]                     entry_req_type_o_13        ;
assign   entry_req_type_o[13] =  entry_req_type_o_13        ;
wire [32-1:0]                    entry_resp_data_o_13       ;
wire [3-1:0]                     entry_req_info_o_13        ;
wire [32-1:0]                    entry_addr_o_14            ;
wire [5:0]           entry_inst_id_o_14         ;
wire                             entry_vld_o_14             ;
wire [4-1:0]                     entry_req_state_o_14       ;
wire [1-1:0]                     entry_req_type_o_14        ;
assign   entry_req_type_o[14] =  entry_req_type_o_14        ;
wire [32-1:0]                    entry_resp_data_o_14       ;
wire [3-1:0]                     entry_req_info_o_14        ;
wire [32-1:0]                    entry_addr_o_15            ;
wire [5:0]           entry_inst_id_o_15         ;
wire                             entry_vld_o_15             ;
wire [4-1:0]                     entry_req_state_o_15       ;
wire [1-1:0]                     entry_req_type_o_15        ;
assign   entry_req_type_o[15] =  entry_req_type_o_15        ;
wire [32-1:0]                    entry_resp_data_o_15       ;
wire [3-1:0]                     entry_req_info_o_15        ;


wire [16-1:0]           wait_state         ;
wire [16-1:0]           dev_wait_state     =(~entry_req_type_o) &wait_state;
wire [16-1:0]           mem_wait_state     =( entry_req_type_o) &wait_state;
wire [16-1:0]           vld_entry          ;
// wire [16-1:0]           empty_entry        ~vld_entry;

wire [16-1:0]           mem_aces_state     ;
wire [16-1:0]           dev_aces_state     ;
wire [16-1:0]           cache_miss_state   ;
wire [16-1:0]           ddr_aces_state     ;
wire [16-1:0]           ready_state        ;
wire [16-1:0]           dev_arready_state  ;


wire                                mem_selector_en    =!dmem_load_req;
wire                                dev_selector_en    =dev_aces_state==0 & dev_arready_state==0 & (~dev_arvalid);
wire                                ddr_selector_en    =ddr_aces_state==0;
wire                                resp_selector_en   =1'b1;


wire [$clog2(16)-1:0]   in_selector_out,mem_selector_out,dev_selector_out,ddr_selector_out,resp_selector_out;
idle_select_comp                    in_selector    (vld_entry,in_selector_out);
RR_arbiter                          mem_selector   (.clk(clk),.rst_n(rst_n),.enable(mem_selector_en),.req(mem_wait_state)  ,.grant_out(mem_selector_out) );
RR_arbiter                          dev_selector   (.clk(clk),.rst_n(rst_n),.enable(dev_selector_en),.req(dev_wait_state)  ,.grant_out(dev_selector_out) );
RR_arbiter                          ddr_selector   (.clk(clk),.rst_n(rst_n),.enable(ddr_selector_en),.req(cache_miss_state),.grant_out(ddr_selector_out) );
RR_arbiter                          resp_selector  (.clk(clk),.rst_n(rst_n),.enable(resp_selector_en),.req(ready_state)     ,.grant_out(resp_selector_out));

wire [16-1:0]           load_flush_selected ;
wire [16-1:0]           flush_in_selected   =lsu_flush? load_flush_selected :0;
wire [16-1:0]           new_req_in_selected =((vld_entry!={16{1'b1}})&&(lsu_load_req))? 2**in_selector_out :0;
wire new_req_cmpo_res;
rob_id_cmpo #(.DW(5+1))   new_req_cmpo        (lsu_flush_id,lsu_inst_id,new_req_cmpo_res);
// wire [16-1:0]           new_req_in_flag     ={16{!lsu_flush ? 1'b1: lsu_inst_id>lsu_flush_id? 1'b0:1'b1}};
wire [16-1:0]           new_req_in_flag     ={16{!lsu_flush ? 1'b1: new_req_cmpo_res? 1'b0:1'b1}};

wire [16-1:0]           load_in_selected    =(new_req_in_selected & new_req_in_flag);

wire [16-1:0]           load_mem_selected   =mem_wait_state[mem_selector_out]  ? 2**mem_selector_out :0;
wire [16-1:0]           load_dev_selected   =dev_wait_state[dev_selector_out]  ? 2**dev_selector_out :0;
wire [16-1:0]           load_resp_selected  =ready_state[resp_selector_out]    ? 2**resp_selector_out:0;

wire [16-1:0]           load_ddr_selected   =cache_miss_state[ddr_selector_out] ? 2**ddr_selector_out:0;
wire [16-1:0]           load_RAW_selected   =(new_req_in_selected & new_req_in_flag) & {16{RAW_flag}} ;

wire [16-1:0]           load_cache_miss     =dmem_load_ack? 0:2**mem_selector_out;
wire [16-1:0]           load_cache_hit      =dmem_load_ack? 2**mem_selector_out:0;
wire [16-1:0]           load_ddr_ack        =ddr_load_ack ? 2**ddr_selector_out:0;

wire [16-1:0]           load_dev_arready    =dev_arready?2**dev_selector_out:0;
wire [16-1:0]           load_dev_rvalid     =dev_rvalid ?2**dev_selector_out:0;
wire [16-1:0]           load_dev_rresp      =dev_rresp  ?2**dev_selector_out:0;


wire [32-1:0]                       load_addr           =lsu_op1_val+lsu_op2_val;
wire [5:0]              load_inst_id        =lsu_inst_id;
wire [2-1:0]                        load_req_type       =load_addr >32'h8000_0000;  //1:mem 0:dev
wire [2-1:0]                        load_req_width_type =lsu_ctrl_byte? 2:
                                                         lsu_ctrl_half? 1:
                                                         lsu_ctrl_word? 0:3;
wire [3-1:0]                        load_req_info       ={lsu_ctrl_unsign,load_req_width_type};


wire [32-1:0]                       resp_load_data;
wire [5:0]              resp_inst_id  ;
wire [3-1:0]                        resp_load_info;
wire [32-1:0]                       resp_load_addr;

wire [32-1:0]                       dev_load_addr;

assign      lsu_load_ready     =vld_entry!={16{1'b1}};

//dmem
assign      dmem_load_req      =load_mem_selected !=0;
// assign      dmem_load_flush    =      ;
//ddr
assign      ddr_load_req       =load_ddr_selected !=0;
// assign      ddr_load_req_tid   =
//dev
assign      dev_arvalid        =(load_dev_selected !=0) | (dev_aces_state!=0);
assign      dev_rready         =dev_arready_state  !=0;
assign      dev_araddr         =dev_load_addr;


//resp
    wire lb_00,lbu_00;
    wire lb_01,lbu_01;
    wire lb_10,lbu_10;
    wire lb_11,lbu_11;

    wire lh_00,lhu_00;
    wire lh_10,lhu_10;

    wire ctrl_unsign=resp_load_info[2];
    wire ctrl_byte  =resp_load_info[1:0]==2;
    wire ctrl_half  =resp_load_info[1:0]==1;
    wire ctrl_word  =resp_load_info[1:0]==0;

    wire [31:0] byte_resp_data;
    wire [31:0] byte_resp_datau;
    wire [31:0] half_resp_data;
    wire [31:0] half_resp_datau;
    wire [31:0] word_resp_data;
    wire [31:0] mem_resp_data;
    assign lb_00  = resp_load_addr[1:0] == 2'b00;
    assign lb_01  = resp_load_addr[1:0] == 2'b01;
    assign lb_10  = resp_load_addr[1:0] == 2'b10;
    assign lb_11  = resp_load_addr[1:0] == 2'b11;

    assign lbu_00 = lb_00 & ctrl_unsign; 
    assign lbu_01 = lb_01 & ctrl_unsign; 
    assign lbu_10 = lb_10 & ctrl_unsign; 
    assign lbu_11 = lb_11 & ctrl_unsign; 

    assign lh_00  = resp_load_addr == 2'b00;
    assign lh_10  = resp_load_addr == 2'b10;

    assign lhu_00 = lh_00 & ctrl_unsign;
    assign lhu_10 = lh_10 & ctrl_unsign;

    assign byte_resp_data  = {32{lb_00}} & {{24{resp_load_data[7]} },resp_load_data[7:0]} |
                             {32{lb_01}} & {{24{resp_load_data[15]}},resp_load_data[15:8]} |
                             {32{lb_10}} & {{24{resp_load_data[23]}},resp_load_data[23:16]} |
                             {32{lb_11}} & {{24{resp_load_data[31]}},resp_load_data[31:24]} ;

    assign byte_resp_datau = {32{lbu_00}} & {24'b0,resp_load_data[7:0]  } |
                             {32{lbu_01}} & {24'b0,resp_load_data[15:8] } |
                             {32{lbu_10}} & {24'b0,resp_load_data[23:16]} |
                             {32{lbu_11}} & {24'b0,resp_load_data[31:24]} ;

    assign half_resp_data  = {32{lhu_00}} & {{16{resp_load_data[15]}},resp_load_data[15:0]} |
                             {32{lhu_00}} & {{16{resp_load_data[31]}},resp_load_data[31:16]} ;

    assign half_resp_datau = {32{lhu_00}} & {16'b0,resp_load_data[15:0]} |
                             {32{lhu_00}} & {16'b0,resp_load_data[31:16]} ;

    assign word_resp_data = resp_load_data;

    assign mem_resp_data = {32{ctrl_byte & ~ctrl_unsign}} & byte_resp_data |
                           {32{ctrl_byte & ctrl_unsign}} & byte_resp_datau |
                           {32{ctrl_half & ~ctrl_unsign}} & half_resp_data |
                           {32{ctrl_half & ctrl_unsign}} & half_resp_datau |
                           {32{ctrl_word}} & word_resp_data;


assign                   lsu_resp_inst_id =resp_inst_id;
assign                   lsu_resp_vld     =load_resp_selected !=0;
assign                   lsu_resp_rd_vld  =1'b1             ;
assign                   lsu_resp_rd_ind  =0                ;
assign                   lsu_resp_rd_val  =mem_resp_data    ;
assign                   lsu_exp_vld      =0                ;

assign resp_load_data =
({32{resp_selector_out==0}} & entry_resp_data_o_0)|
({32{resp_selector_out==1}} & entry_resp_data_o_1)|
({32{resp_selector_out==2}} & entry_resp_data_o_2)|
({32{resp_selector_out==3}} & entry_resp_data_o_3)|
({32{resp_selector_out==4}} & entry_resp_data_o_4)|
({32{resp_selector_out==5}} & entry_resp_data_o_5)|
({32{resp_selector_out==6}} & entry_resp_data_o_6)|
({32{resp_selector_out==7}} & entry_resp_data_o_7)|
({32{resp_selector_out==8}} & entry_resp_data_o_8)|
({32{resp_selector_out==9}} & entry_resp_data_o_9)|
({32{resp_selector_out==10}} & entry_resp_data_o_10)|
({32{resp_selector_out==11}} & entry_resp_data_o_11)|
({32{resp_selector_out==12}} & entry_resp_data_o_12)|
({32{resp_selector_out==13}} & entry_resp_data_o_13)|
({32{resp_selector_out==14}} & entry_resp_data_o_14)|
({32{resp_selector_out==15}} & entry_resp_data_o_15);

assign resp_inst_id =
({32{resp_selector_out==0}} & entry_inst_id_o_0)|
({32{resp_selector_out==1}} & entry_inst_id_o_1)|
({32{resp_selector_out==2}} & entry_inst_id_o_2)|
({32{resp_selector_out==3}} & entry_inst_id_o_3)|
({32{resp_selector_out==4}} & entry_inst_id_o_4)|
({32{resp_selector_out==5}} & entry_inst_id_o_5)|
({32{resp_selector_out==6}} & entry_inst_id_o_6)|
({32{resp_selector_out==7}} & entry_inst_id_o_7)|
({32{resp_selector_out==8}} & entry_inst_id_o_8)|
({32{resp_selector_out==9}} & entry_inst_id_o_9)|
({32{resp_selector_out==10}} & entry_inst_id_o_10)|
({32{resp_selector_out==11}} & entry_inst_id_o_11)|
({32{resp_selector_out==12}} & entry_inst_id_o_12)|
({32{resp_selector_out==13}} & entry_inst_id_o_13)|
({32{resp_selector_out==14}} & entry_inst_id_o_14)|
({32{resp_selector_out==15}} & entry_inst_id_o_15);

assign resp_load_info =
({32{resp_selector_out==0}} & entry_req_info_o_0)|
({32{resp_selector_out==1}} & entry_req_info_o_1)|
({32{resp_selector_out==2}} & entry_req_info_o_2)|
({32{resp_selector_out==3}} & entry_req_info_o_3)|
({32{resp_selector_out==4}} & entry_req_info_o_4)|
({32{resp_selector_out==5}} & entry_req_info_o_5)|
({32{resp_selector_out==6}} & entry_req_info_o_6)|
({32{resp_selector_out==7}} & entry_req_info_o_7)|
({32{resp_selector_out==8}} & entry_req_info_o_8)|
({32{resp_selector_out==9}} & entry_req_info_o_9)|
({32{resp_selector_out==10}} & entry_req_info_o_10)|
({32{resp_selector_out==11}} & entry_req_info_o_11)|
({32{resp_selector_out==12}} & entry_req_info_o_12)|
({32{resp_selector_out==13}} & entry_req_info_o_13)|
({32{resp_selector_out==14}} & entry_req_info_o_14)|
({32{resp_selector_out==15}} & entry_req_info_o_15);

assign resp_load_addr =
({32{resp_selector_out==0}} & entry_addr_o_0 )|
({32{resp_selector_out==1}} & entry_addr_o_1 )|
({32{resp_selector_out==2}} & entry_addr_o_2 )|
({32{resp_selector_out==3}} & entry_addr_o_3 )|
({32{resp_selector_out==4}} & entry_addr_o_4 )|
({32{resp_selector_out==5}} & entry_addr_o_5 )|
({32{resp_selector_out==6}} & entry_addr_o_6 )|
({32{resp_selector_out==7}} & entry_addr_o_7 )|
({32{resp_selector_out==8}} & entry_addr_o_8 )|
({32{resp_selector_out==9}} & entry_addr_o_9 )|
({32{resp_selector_out==10}} & entry_addr_o_10 )|
({32{resp_selector_out==11}} & entry_addr_o_11 )|
({32{resp_selector_out==12}} & entry_addr_o_12 )|
({32{resp_selector_out==13}} & entry_addr_o_13 )|
({32{resp_selector_out==14}} & entry_addr_o_14 )|
({32{resp_selector_out==15}} & entry_addr_o_15);
//queue ctrl
wire                       entry_in_selected_0          =load_in_selected[0]   ;
wire                       entry_mem_selected_0         =load_mem_selected[0]  ;
wire                       entry_dev_selected_0         =load_dev_selected[0]  ;
wire                       entry_resp_selected_0        =load_resp_selected[0] ;
wire                       entry_ddr_selected_0         =load_ddr_selected[0]  ;
wire                       entry_RAW_selected_0         =load_RAW_selected[0]  ;
wire                       entry_flush_selected_0       =flush_in_selected[0]  ;
wire                       entry_cache_miss_0           =load_cache_miss[0]    ;
wire                       entry_cache_hit_0            =load_cache_hit[0]     ;
wire                       entry_ddr_ack_0              =load_ddr_ack[0]       ;
wire                       entry_dev_arready_0          =load_dev_arready[0]   ;
wire                       entry_dev_rvalid_0           =load_dev_rvalid[0]    ;
wire                       entry_dev_rresp_0            =load_dev_rresp[0]     ;
wire                       entry_in_selected_1          =load_in_selected[1]   ;
wire                       entry_mem_selected_1         =load_mem_selected[1]  ;
wire                       entry_dev_selected_1         =load_dev_selected[1]  ;
wire                       entry_resp_selected_1        =load_resp_selected[1] ;
wire                       entry_ddr_selected_1         =load_ddr_selected[1]  ;
wire                       entry_RAW_selected_1         =load_RAW_selected[1]  ;
wire                       entry_flush_selected_1       =flush_in_selected[1]  ;
wire                       entry_cache_miss_1           =load_cache_miss[1]    ;
wire                       entry_cache_hit_1            =load_cache_hit[1]     ;
wire                       entry_ddr_ack_1              =load_ddr_ack[1]       ;
wire                       entry_dev_arready_1          =load_dev_arready[1]   ;
wire                       entry_dev_rvalid_1           =load_dev_rvalid[1]    ;
wire                       entry_dev_rresp_1            =load_dev_rresp[1]     ;
wire                       entry_in_selected_2          =load_in_selected[2]   ;
wire                       entry_mem_selected_2         =load_mem_selected[2]  ;
wire                       entry_dev_selected_2         =load_dev_selected[2]  ;
wire                       entry_resp_selected_2        =load_resp_selected[2] ;
wire                       entry_ddr_selected_2         =load_ddr_selected[2]  ;
wire                       entry_RAW_selected_2         =load_RAW_selected[2]  ;
wire                       entry_flush_selected_2       =flush_in_selected[2]  ;
wire                       entry_cache_miss_2           =load_cache_miss[2]    ;
wire                       entry_cache_hit_2            =load_cache_hit[2]     ;
wire                       entry_ddr_ack_2              =load_ddr_ack[2]       ;
wire                       entry_dev_arready_2          =load_dev_arready[2]   ;
wire                       entry_dev_rvalid_2           =load_dev_rvalid[2]    ;
wire                       entry_dev_rresp_2            =load_dev_rresp[2]     ;
wire                       entry_in_selected_3          =load_in_selected[3]   ;
wire                       entry_mem_selected_3         =load_mem_selected[3]  ;
wire                       entry_dev_selected_3         =load_dev_selected[3]  ;
wire                       entry_resp_selected_3        =load_resp_selected[3] ;
wire                       entry_ddr_selected_3         =load_ddr_selected[3]  ;
wire                       entry_RAW_selected_3         =load_RAW_selected[3]  ;
wire                       entry_flush_selected_3       =flush_in_selected[3]  ;
wire                       entry_cache_miss_3           =load_cache_miss[3]    ;
wire                       entry_cache_hit_3            =load_cache_hit[3]     ;
wire                       entry_ddr_ack_3              =load_ddr_ack[3]       ;
wire                       entry_dev_arready_3          =load_dev_arready[3]   ;
wire                       entry_dev_rvalid_3           =load_dev_rvalid[3]    ;
wire                       entry_dev_rresp_3            =load_dev_rresp[3]     ;
wire                       entry_in_selected_4          =load_in_selected[4]   ;
wire                       entry_mem_selected_4         =load_mem_selected[4]  ;
wire                       entry_dev_selected_4         =load_dev_selected[4]  ;
wire                       entry_resp_selected_4        =load_resp_selected[4] ;
wire                       entry_ddr_selected_4         =load_ddr_selected[4]  ;
wire                       entry_RAW_selected_4         =load_RAW_selected[4]  ;
wire                       entry_flush_selected_4       =flush_in_selected[4]  ;
wire                       entry_cache_miss_4           =load_cache_miss[4]    ;
wire                       entry_cache_hit_4            =load_cache_hit[4]     ;
wire                       entry_ddr_ack_4              =load_ddr_ack[4]       ;
wire                       entry_dev_arready_4          =load_dev_arready[4]   ;
wire                       entry_dev_rvalid_4           =load_dev_rvalid[4]    ;
wire                       entry_dev_rresp_4            =load_dev_rresp[4]     ;
wire                       entry_in_selected_5          =load_in_selected[5]   ;
wire                       entry_mem_selected_5         =load_mem_selected[5]  ;
wire                       entry_dev_selected_5         =load_dev_selected[5]  ;
wire                       entry_resp_selected_5        =load_resp_selected[5] ;
wire                       entry_ddr_selected_5         =load_ddr_selected[5]  ;
wire                       entry_RAW_selected_5         =load_RAW_selected[5]  ;
wire                       entry_flush_selected_5       =flush_in_selected[5]  ;
wire                       entry_cache_miss_5           =load_cache_miss[5]    ;
wire                       entry_cache_hit_5            =load_cache_hit[5]     ;
wire                       entry_ddr_ack_5              =load_ddr_ack[5]       ;
wire                       entry_dev_arready_5          =load_dev_arready[5]   ;
wire                       entry_dev_rvalid_5           =load_dev_rvalid[5]    ;
wire                       entry_dev_rresp_5            =load_dev_rresp[5]     ;
wire                       entry_in_selected_6          =load_in_selected[6]   ;
wire                       entry_mem_selected_6         =load_mem_selected[6]  ;
wire                       entry_dev_selected_6         =load_dev_selected[6]  ;
wire                       entry_resp_selected_6        =load_resp_selected[6] ;
wire                       entry_ddr_selected_6         =load_ddr_selected[6]  ;
wire                       entry_RAW_selected_6         =load_RAW_selected[6]  ;
wire                       entry_flush_selected_6       =flush_in_selected[6]  ;
wire                       entry_cache_miss_6           =load_cache_miss[6]    ;
wire                       entry_cache_hit_6            =load_cache_hit[6]     ;
wire                       entry_ddr_ack_6              =load_ddr_ack[6]       ;
wire                       entry_dev_arready_6          =load_dev_arready[6]   ;
wire                       entry_dev_rvalid_6           =load_dev_rvalid[6]    ;
wire                       entry_dev_rresp_6            =load_dev_rresp[6]     ;
wire                       entry_in_selected_7          =load_in_selected[7]   ;
wire                       entry_mem_selected_7         =load_mem_selected[7]  ;
wire                       entry_dev_selected_7         =load_dev_selected[7]  ;
wire                       entry_resp_selected_7        =load_resp_selected[7] ;
wire                       entry_ddr_selected_7         =load_ddr_selected[7]  ;
wire                       entry_RAW_selected_7         =load_RAW_selected[7]  ;
wire                       entry_flush_selected_7       =flush_in_selected[7]  ;
wire                       entry_cache_miss_7           =load_cache_miss[7]    ;
wire                       entry_cache_hit_7            =load_cache_hit[7]     ;
wire                       entry_ddr_ack_7              =load_ddr_ack[7]       ;
wire                       entry_dev_arready_7          =load_dev_arready[7]   ;
wire                       entry_dev_rvalid_7           =load_dev_rvalid[7]    ;
wire                       entry_dev_rresp_7            =load_dev_rresp[7]     ;
wire                       entry_in_selected_8          =load_in_selected[8]   ;
wire                       entry_mem_selected_8         =load_mem_selected[8]  ;
wire                       entry_dev_selected_8         =load_dev_selected[8]  ;
wire                       entry_resp_selected_8        =load_resp_selected[8] ;
wire                       entry_ddr_selected_8         =load_ddr_selected[8]  ;
wire                       entry_RAW_selected_8         =load_RAW_selected[8]  ;
wire                       entry_flush_selected_8       =flush_in_selected[8]  ;
wire                       entry_cache_miss_8           =load_cache_miss[8]    ;
wire                       entry_cache_hit_8            =load_cache_hit[8]     ;
wire                       entry_ddr_ack_8              =load_ddr_ack[8]       ;
wire                       entry_dev_arready_8          =load_dev_arready[8]   ;
wire                       entry_dev_rvalid_8           =load_dev_rvalid[8]    ;
wire                       entry_dev_rresp_8            =load_dev_rresp[8]     ;
wire                       entry_in_selected_9          =load_in_selected[9]   ;
wire                       entry_mem_selected_9         =load_mem_selected[9]  ;
wire                       entry_dev_selected_9         =load_dev_selected[9]  ;
wire                       entry_resp_selected_9        =load_resp_selected[9] ;
wire                       entry_ddr_selected_9         =load_ddr_selected[9]  ;
wire                       entry_RAW_selected_9         =load_RAW_selected[9]  ;
wire                       entry_flush_selected_9       =flush_in_selected[9]  ;
wire                       entry_cache_miss_9           =load_cache_miss[9]    ;
wire                       entry_cache_hit_9            =load_cache_hit[9]     ;
wire                       entry_ddr_ack_9              =load_ddr_ack[9]       ;
wire                       entry_dev_arready_9          =load_dev_arready[9]   ;
wire                       entry_dev_rvalid_9           =load_dev_rvalid[9]    ;
wire                       entry_dev_rresp_9            =load_dev_rresp[9]     ;
wire                       entry_in_selected_10          =load_in_selected[10]   ;
wire                       entry_mem_selected_10         =load_mem_selected[10]  ;
wire                       entry_dev_selected_10         =load_dev_selected[10]  ;
wire                       entry_resp_selected_10        =load_resp_selected[10] ;
wire                       entry_ddr_selected_10         =load_ddr_selected[10]  ;
wire                       entry_RAW_selected_10         =load_RAW_selected[10]  ;
wire                       entry_flush_selected_10       =flush_in_selected[10]  ;
wire                       entry_cache_miss_10           =load_cache_miss[10]    ;
wire                       entry_cache_hit_10            =load_cache_hit[10]     ;
wire                       entry_ddr_ack_10              =load_ddr_ack[10]       ;
wire                       entry_dev_arready_10          =load_dev_arready[10]   ;
wire                       entry_dev_rvalid_10           =load_dev_rvalid[10]    ;
wire                       entry_dev_rresp_10            =load_dev_rresp[10]     ;
wire                       entry_in_selected_11          =load_in_selected[11]   ;
wire                       entry_mem_selected_11         =load_mem_selected[11]  ;
wire                       entry_dev_selected_11         =load_dev_selected[11]  ;
wire                       entry_resp_selected_11        =load_resp_selected[11] ;
wire                       entry_ddr_selected_11         =load_ddr_selected[11]  ;
wire                       entry_RAW_selected_11         =load_RAW_selected[11]  ;
wire                       entry_flush_selected_11       =flush_in_selected[11]  ;
wire                       entry_cache_miss_11           =load_cache_miss[11]    ;
wire                       entry_cache_hit_11            =load_cache_hit[11]     ;
wire                       entry_ddr_ack_11              =load_ddr_ack[11]       ;
wire                       entry_dev_arready_11          =load_dev_arready[11]   ;
wire                       entry_dev_rvalid_11           =load_dev_rvalid[11]    ;
wire                       entry_dev_rresp_11            =load_dev_rresp[11]     ;
wire                       entry_in_selected_12          =load_in_selected[12]   ;
wire                       entry_mem_selected_12         =load_mem_selected[12]  ;
wire                       entry_dev_selected_12         =load_dev_selected[12]  ;
wire                       entry_resp_selected_12        =load_resp_selected[12] ;
wire                       entry_ddr_selected_12         =load_ddr_selected[12]  ;
wire                       entry_RAW_selected_12         =load_RAW_selected[12]  ;
wire                       entry_flush_selected_12       =flush_in_selected[12]  ;
wire                       entry_cache_miss_12           =load_cache_miss[12]    ;
wire                       entry_cache_hit_12            =load_cache_hit[12]     ;
wire                       entry_ddr_ack_12              =load_ddr_ack[12]       ;
wire                       entry_dev_arready_12          =load_dev_arready[12]   ;
wire                       entry_dev_rvalid_12           =load_dev_rvalid[12]    ;
wire                       entry_dev_rresp_12            =load_dev_rresp[12]     ;
wire                       entry_in_selected_13          =load_in_selected[13]   ;
wire                       entry_mem_selected_13         =load_mem_selected[13]  ;
wire                       entry_dev_selected_13         =load_dev_selected[13]  ;
wire                       entry_resp_selected_13        =load_resp_selected[13] ;
wire                       entry_ddr_selected_13         =load_ddr_selected[13]  ;
wire                       entry_RAW_selected_13         =load_RAW_selected[13]  ;
wire                       entry_flush_selected_13       =flush_in_selected[13]  ;
wire                       entry_cache_miss_13           =load_cache_miss[13]    ;
wire                       entry_cache_hit_13            =load_cache_hit[13]     ;
wire                       entry_ddr_ack_13              =load_ddr_ack[13]       ;
wire                       entry_dev_arready_13          =load_dev_arready[13]   ;
wire                       entry_dev_rvalid_13           =load_dev_rvalid[13]    ;
wire                       entry_dev_rresp_13            =load_dev_rresp[13]     ;
wire                       entry_in_selected_14          =load_in_selected[14]   ;
wire                       entry_mem_selected_14         =load_mem_selected[14]  ;
wire                       entry_dev_selected_14         =load_dev_selected[14]  ;
wire                       entry_resp_selected_14        =load_resp_selected[14] ;
wire                       entry_ddr_selected_14         =load_ddr_selected[14]  ;
wire                       entry_RAW_selected_14         =load_RAW_selected[14]  ;
wire                       entry_flush_selected_14       =flush_in_selected[14]  ;
wire                       entry_cache_miss_14           =load_cache_miss[14]    ;
wire                       entry_cache_hit_14            =load_cache_hit[14]     ;
wire                       entry_ddr_ack_14              =load_ddr_ack[14]       ;
wire                       entry_dev_arready_14          =load_dev_arready[14]   ;
wire                       entry_dev_rvalid_14           =load_dev_rvalid[14]    ;
wire                       entry_dev_rresp_14            =load_dev_rresp[14]     ;
wire                       entry_in_selected_15          =load_in_selected[15]   ;
wire                       entry_mem_selected_15         =load_mem_selected[15]  ;
wire                       entry_dev_selected_15         =load_dev_selected[15]  ;
wire                       entry_resp_selected_15        =load_resp_selected[15] ;
wire                       entry_ddr_selected_15         =load_ddr_selected[15]  ;
wire                       entry_RAW_selected_15         =load_RAW_selected[15]  ;
wire                       entry_flush_selected_15       =flush_in_selected[15]  ;
wire                       entry_cache_miss_15           =load_cache_miss[15]    ;
wire                       entry_cache_hit_15            =load_cache_hit[15]     ;
wire                       entry_ddr_ack_15              =load_ddr_ack[15]       ;
wire                       entry_dev_arready_15          =load_dev_arready[15]   ;
wire                       entry_dev_rvalid_15           =load_dev_rvalid[15]    ;
wire                       entry_dev_rresp_15            =load_dev_rresp[15]     ;

//item in
wire [32-1:0]                    entry_addr_0           =load_addr          ;
wire [5:0]           entry_inst_id_0        =load_inst_id       ;
wire [1-1:0]                     entry_req_type_0       =load_req_type      ;
wire [3-1:0]                     entry_req_info_0       =load_req_info      ;
wire [32-1:0]                    entry_resp_data_0      = load_RAW_selected[0] ? RAW_data        :                    
                                                           ~entry_req_type_o_0   ? dev_rdata       :                    
                                                           mem_aces_state[0]    ? dmem_load_rdata :                    
                                                           ddr_aces_state[0]    ? ddr_load_rdata  :0                  ;
wire [32-1:0]                    entry_addr_1           =load_addr          ;
wire [5:0]           entry_inst_id_1        =load_inst_id       ;
wire [1-1:0]                     entry_req_type_1       =load_req_type      ;
wire [3-1:0]                     entry_req_info_1       =load_req_info      ;
wire [32-1:0]                    entry_resp_data_1      = load_RAW_selected[1] ? RAW_data        :                    
                                                           ~entry_req_type_o_1   ? dev_rdata       :                    
                                                           mem_aces_state[1]    ? dmem_load_rdata :                    
                                                           ddr_aces_state[1]    ? ddr_load_rdata  :0                  ;
wire [32-1:0]                    entry_addr_2           =load_addr          ;
wire [5:0]           entry_inst_id_2        =load_inst_id       ;
wire [1-1:0]                     entry_req_type_2       =load_req_type      ;
wire [3-1:0]                     entry_req_info_2       =load_req_info      ;
wire [32-1:0]                    entry_resp_data_2      = load_RAW_selected[2] ? RAW_data        :                    
                                                           ~entry_req_type_o_2   ? dev_rdata       :                    
                                                           mem_aces_state[2]    ? dmem_load_rdata :                    
                                                           ddr_aces_state[2]    ? ddr_load_rdata  :0                  ;
wire [32-1:0]                    entry_addr_3           =load_addr          ;
wire [5:0]           entry_inst_id_3        =load_inst_id       ;
wire [1-1:0]                     entry_req_type_3       =load_req_type      ;
wire [3-1:0]                     entry_req_info_3       =load_req_info      ;
wire [32-1:0]                    entry_resp_data_3      = load_RAW_selected[3] ? RAW_data        :                    
                                                           ~entry_req_type_o_3   ? dev_rdata       :                    
                                                           mem_aces_state[3]    ? dmem_load_rdata :                    
                                                           ddr_aces_state[3]    ? ddr_load_rdata  :0                  ;
wire [32-1:0]                    entry_addr_4           =load_addr          ;
wire [5:0]           entry_inst_id_4        =load_inst_id       ;
wire [1-1:0]                     entry_req_type_4       =load_req_type      ;
wire [3-1:0]                     entry_req_info_4       =load_req_info      ;
wire [32-1:0]                    entry_resp_data_4      = load_RAW_selected[4] ? RAW_data        :                    
                                                           ~entry_req_type_o_4   ? dev_rdata       :                    
                                                           mem_aces_state[4]    ? dmem_load_rdata :                    
                                                           ddr_aces_state[4]    ? ddr_load_rdata  :0                  ;
wire [32-1:0]                    entry_addr_5           =load_addr          ;
wire [5:0]           entry_inst_id_5        =load_inst_id       ;
wire [1-1:0]                     entry_req_type_5       =load_req_type      ;
wire [3-1:0]                     entry_req_info_5       =load_req_info      ;
wire [32-1:0]                    entry_resp_data_5      = load_RAW_selected[5] ? RAW_data        :                    
                                                           ~entry_req_type_o_5   ? dev_rdata       :                    
                                                           mem_aces_state[5]    ? dmem_load_rdata :                    
                                                           ddr_aces_state[5]    ? ddr_load_rdata  :0                  ;
wire [32-1:0]                    entry_addr_6           =load_addr          ;
wire [5:0]           entry_inst_id_6        =load_inst_id       ;
wire [1-1:0]                     entry_req_type_6       =load_req_type      ;
wire [3-1:0]                     entry_req_info_6       =load_req_info      ;
wire [32-1:0]                    entry_resp_data_6      = load_RAW_selected[6] ? RAW_data        :                    
                                                           ~entry_req_type_o_6   ? dev_rdata       :                    
                                                           mem_aces_state[6]    ? dmem_load_rdata :                    
                                                           ddr_aces_state[6]    ? ddr_load_rdata  :0                  ;
wire [32-1:0]                    entry_addr_7           =load_addr          ;
wire [5:0]           entry_inst_id_7        =load_inst_id       ;
wire [1-1:0]                     entry_req_type_7       =load_req_type      ;
wire [3-1:0]                     entry_req_info_7       =load_req_info      ;
wire [32-1:0]                    entry_resp_data_7      = load_RAW_selected[7] ? RAW_data        :                    
                                                           ~entry_req_type_o_7   ? dev_rdata       :                    
                                                           mem_aces_state[7]    ? dmem_load_rdata :                    
                                                           ddr_aces_state[7]    ? ddr_load_rdata  :0                  ;
wire [32-1:0]                    entry_addr_8           =load_addr          ;
wire [5:0]           entry_inst_id_8        =load_inst_id       ;
wire [1-1:0]                     entry_req_type_8       =load_req_type      ;
wire [3-1:0]                     entry_req_info_8       =load_req_info      ;
wire [32-1:0]                    entry_resp_data_8      = load_RAW_selected[8] ? RAW_data        :                    
                                                           ~entry_req_type_o_8   ? dev_rdata       :                    
                                                           mem_aces_state[8]    ? dmem_load_rdata :                    
                                                           ddr_aces_state[8]    ? ddr_load_rdata  :0                  ;
wire [32-1:0]                    entry_addr_9           =load_addr          ;
wire [5:0]           entry_inst_id_9        =load_inst_id       ;
wire [1-1:0]                     entry_req_type_9       =load_req_type      ;
wire [3-1:0]                     entry_req_info_9       =load_req_info      ;
wire [32-1:0]                    entry_resp_data_9      = load_RAW_selected[9] ? RAW_data        :                    
                                                           ~entry_req_type_o_9   ? dev_rdata       :                    
                                                           mem_aces_state[9]    ? dmem_load_rdata :                    
                                                           ddr_aces_state[9]    ? ddr_load_rdata  :0                  ;
wire [32-1:0]                    entry_addr_10           =load_addr          ;
wire [5:0]           entry_inst_id_10        =load_inst_id       ;
wire [1-1:0]                     entry_req_type_10       =load_req_type      ;
wire [3-1:0]                     entry_req_info_10       =load_req_info      ;
wire [32-1:0]                    entry_resp_data_10      = load_RAW_selected[10] ? RAW_data        :                    
                                                           ~entry_req_type_o_10   ? dev_rdata       :                    
                                                           mem_aces_state[10]    ? dmem_load_rdata :                    
                                                           ddr_aces_state[10]    ? ddr_load_rdata  :0                  ;
wire [32-1:0]                    entry_addr_11           =load_addr          ;
wire [5:0]           entry_inst_id_11        =load_inst_id       ;
wire [1-1:0]                     entry_req_type_11       =load_req_type      ;
wire [3-1:0]                     entry_req_info_11       =load_req_info      ;
wire [32-1:0]                    entry_resp_data_11      = load_RAW_selected[11] ? RAW_data        :                    
                                                           ~entry_req_type_o_11   ? dev_rdata       :                    
                                                           mem_aces_state[11]    ? dmem_load_rdata :                    
                                                           ddr_aces_state[11]    ? ddr_load_rdata  :0                  ;
wire [32-1:0]                    entry_addr_12           =load_addr          ;
wire [5:0]           entry_inst_id_12        =load_inst_id       ;
wire [1-1:0]                     entry_req_type_12       =load_req_type      ;
wire [3-1:0]                     entry_req_info_12       =load_req_info      ;
wire [32-1:0]                    entry_resp_data_12      = load_RAW_selected[12] ? RAW_data        :                    
                                                           ~entry_req_type_o_12   ? dev_rdata       :                    
                                                           mem_aces_state[12]    ? dmem_load_rdata :                    
                                                           ddr_aces_state[12]    ? ddr_load_rdata  :0                  ;
wire [32-1:0]                    entry_addr_13           =load_addr          ;
wire [5:0]           entry_inst_id_13        =load_inst_id       ;
wire [1-1:0]                     entry_req_type_13       =load_req_type      ;
wire [3-1:0]                     entry_req_info_13       =load_req_info      ;
wire [32-1:0]                    entry_resp_data_13      = load_RAW_selected[13] ? RAW_data        :                    
                                                           ~entry_req_type_o_13   ? dev_rdata       :                    
                                                           mem_aces_state[13]    ? dmem_load_rdata :                    
                                                           ddr_aces_state[13]    ? ddr_load_rdata  :0                  ;
wire [32-1:0]                    entry_addr_14           =load_addr          ;
wire [5:0]           entry_inst_id_14        =load_inst_id       ;
wire [1-1:0]                     entry_req_type_14       =load_req_type      ;
wire [3-1:0]                     entry_req_info_14       =load_req_info      ;
wire [32-1:0]                    entry_resp_data_14      = load_RAW_selected[14] ? RAW_data        :                    
                                                           ~entry_req_type_o_14   ? dev_rdata       :                    
                                                           mem_aces_state[14]    ? dmem_load_rdata :                    
                                                           ddr_aces_state[14]    ? ddr_load_rdata  :0                  ;
wire [32-1:0]                    entry_addr_15           =load_addr          ;
wire [5:0]           entry_inst_id_15        =load_inst_id       ;
wire [1-1:0]                     entry_req_type_15       =load_req_type      ;
wire [3-1:0]                     entry_req_info_15       =load_req_info      ;
wire [32-1:0]                    entry_resp_data_15      = load_RAW_selected[15] ? RAW_data        :                    
                                                           ~entry_req_type_o_15   ? dev_rdata       :                    
                                                           mem_aces_state[15]    ? dmem_load_rdata :                    
                                                           ddr_aces_state[15]    ? ddr_load_rdata  :0                  ;






//entry states
assign vld_entry[0]           =entry_vld_o_0                               ;
assign wait_state[0]          =entry_req_state_o_0==1                      ;
assign mem_aces_state[0]      =entry_req_state_o_0==2                      ;
assign dev_aces_state[0]      =entry_req_state_o_0==3                      ;
assign cache_miss_state[0]    =entry_req_state_o_0==4                      ;
assign ddr_aces_state[0]      =entry_req_state_o_0==5                      ;
assign ready_state[0]         =entry_req_state_o_0==6                      ;
assign dev_arready_state[0]   =entry_req_state_o_0==7                      ;
rob_id_cmpo #(.DW(5+1)) load_flush_selected_cmpo_0 (lsu_flush_id,entry_inst_id_o_0,load_flush_selected[0]);
assign vld_entry[1]           =entry_vld_o_1                               ;
assign wait_state[1]          =entry_req_state_o_1==1                      ;
assign mem_aces_state[1]      =entry_req_state_o_1==2                      ;
assign dev_aces_state[1]      =entry_req_state_o_1==3                      ;
assign cache_miss_state[1]    =entry_req_state_o_1==4                      ;
assign ddr_aces_state[1]      =entry_req_state_o_1==5                      ;
assign ready_state[1]         =entry_req_state_o_1==6                      ;
assign dev_arready_state[1]   =entry_req_state_o_1==7                      ;
rob_id_cmpo #(.DW(5+1)) load_flush_selected_cmpo_1 (lsu_flush_id,entry_inst_id_o_1,load_flush_selected[1]);
assign vld_entry[2]           =entry_vld_o_2                               ;
assign wait_state[2]          =entry_req_state_o_2==1                      ;
assign mem_aces_state[2]      =entry_req_state_o_2==2                      ;
assign dev_aces_state[2]      =entry_req_state_o_2==3                      ;
assign cache_miss_state[2]    =entry_req_state_o_2==4                      ;
assign ddr_aces_state[2]      =entry_req_state_o_2==5                      ;
assign ready_state[2]         =entry_req_state_o_2==6                      ;
assign dev_arready_state[2]   =entry_req_state_o_2==7                      ;
rob_id_cmpo #(.DW(5+1)) load_flush_selected_cmpo_2 (lsu_flush_id,entry_inst_id_o_2,load_flush_selected[2]);
assign vld_entry[3]           =entry_vld_o_3                               ;
assign wait_state[3]          =entry_req_state_o_3==1                      ;
assign mem_aces_state[3]      =entry_req_state_o_3==2                      ;
assign dev_aces_state[3]      =entry_req_state_o_3==3                      ;
assign cache_miss_state[3]    =entry_req_state_o_3==4                      ;
assign ddr_aces_state[3]      =entry_req_state_o_3==5                      ;
assign ready_state[3]         =entry_req_state_o_3==6                      ;
assign dev_arready_state[3]   =entry_req_state_o_3==7                      ;
rob_id_cmpo #(.DW(5+1)) load_flush_selected_cmpo_3 (lsu_flush_id,entry_inst_id_o_3,load_flush_selected[3]);
assign vld_entry[4]           =entry_vld_o_4                               ;
assign wait_state[4]          =entry_req_state_o_4==1                      ;
assign mem_aces_state[4]      =entry_req_state_o_4==2                      ;
assign dev_aces_state[4]      =entry_req_state_o_4==3                      ;
assign cache_miss_state[4]    =entry_req_state_o_4==4                      ;
assign ddr_aces_state[4]      =entry_req_state_o_4==5                      ;
assign ready_state[4]         =entry_req_state_o_4==6                      ;
assign dev_arready_state[4]   =entry_req_state_o_4==7                      ;
rob_id_cmpo #(.DW(5+1)) load_flush_selected_cmpo_4 (lsu_flush_id,entry_inst_id_o_4,load_flush_selected[4]);
assign vld_entry[5]           =entry_vld_o_5                               ;
assign wait_state[5]          =entry_req_state_o_5==1                      ;
assign mem_aces_state[5]      =entry_req_state_o_5==2                      ;
assign dev_aces_state[5]      =entry_req_state_o_5==3                      ;
assign cache_miss_state[5]    =entry_req_state_o_5==4                      ;
assign ddr_aces_state[5]      =entry_req_state_o_5==5                      ;
assign ready_state[5]         =entry_req_state_o_5==6                      ;
assign dev_arready_state[5]   =entry_req_state_o_5==7                      ;
rob_id_cmpo #(.DW(5+1)) load_flush_selected_cmpo_5 (lsu_flush_id,entry_inst_id_o_5,load_flush_selected[5]);
assign vld_entry[6]           =entry_vld_o_6                               ;
assign wait_state[6]          =entry_req_state_o_6==1                      ;
assign mem_aces_state[6]      =entry_req_state_o_6==2                      ;
assign dev_aces_state[6]      =entry_req_state_o_6==3                      ;
assign cache_miss_state[6]    =entry_req_state_o_6==4                      ;
assign ddr_aces_state[6]      =entry_req_state_o_6==5                      ;
assign ready_state[6]         =entry_req_state_o_6==6                      ;
assign dev_arready_state[6]   =entry_req_state_o_6==7                      ;
rob_id_cmpo #(.DW(5+1)) load_flush_selected_cmpo_6 (lsu_flush_id,entry_inst_id_o_6,load_flush_selected[6]);
assign vld_entry[7]           =entry_vld_o_7                               ;
assign wait_state[7]          =entry_req_state_o_7==1                      ;
assign mem_aces_state[7]      =entry_req_state_o_7==2                      ;
assign dev_aces_state[7]      =entry_req_state_o_7==3                      ;
assign cache_miss_state[7]    =entry_req_state_o_7==4                      ;
assign ddr_aces_state[7]      =entry_req_state_o_7==5                      ;
assign ready_state[7]         =entry_req_state_o_7==6                      ;
assign dev_arready_state[7]   =entry_req_state_o_7==7                      ;
rob_id_cmpo #(.DW(5+1)) load_flush_selected_cmpo_7 (lsu_flush_id,entry_inst_id_o_7,load_flush_selected[7]);
assign vld_entry[8]           =entry_vld_o_8                               ;
assign wait_state[8]          =entry_req_state_o_8==1                      ;
assign mem_aces_state[8]      =entry_req_state_o_8==2                      ;
assign dev_aces_state[8]      =entry_req_state_o_8==3                      ;
assign cache_miss_state[8]    =entry_req_state_o_8==4                      ;
assign ddr_aces_state[8]      =entry_req_state_o_8==5                      ;
assign ready_state[8]         =entry_req_state_o_8==6                      ;
assign dev_arready_state[8]   =entry_req_state_o_8==7                      ;
rob_id_cmpo #(.DW(5+1)) load_flush_selected_cmpo_8 (lsu_flush_id,entry_inst_id_o_8,load_flush_selected[8]);
assign vld_entry[9]           =entry_vld_o_9                               ;
assign wait_state[9]          =entry_req_state_o_9==1                      ;
assign mem_aces_state[9]      =entry_req_state_o_9==2                      ;
assign dev_aces_state[9]      =entry_req_state_o_9==3                      ;
assign cache_miss_state[9]    =entry_req_state_o_9==4                      ;
assign ddr_aces_state[9]      =entry_req_state_o_9==5                      ;
assign ready_state[9]         =entry_req_state_o_9==6                      ;
assign dev_arready_state[9]   =entry_req_state_o_9==7                      ;
rob_id_cmpo #(.DW(5+1)) load_flush_selected_cmpo_9 (lsu_flush_id,entry_inst_id_o_9,load_flush_selected[9]);
assign vld_entry[10]           =entry_vld_o_10                               ;
assign wait_state[10]          =entry_req_state_o_10==1                      ;
assign mem_aces_state[10]      =entry_req_state_o_10==2                      ;
assign dev_aces_state[10]      =entry_req_state_o_10==3                      ;
assign cache_miss_state[10]    =entry_req_state_o_10==4                      ;
assign ddr_aces_state[10]      =entry_req_state_o_10==5                      ;
assign ready_state[10]         =entry_req_state_o_10==6                      ;
assign dev_arready_state[10]   =entry_req_state_o_10==7                      ;
rob_id_cmpo #(.DW(5+1)) load_flush_selected_cmpo_10 (lsu_flush_id,entry_inst_id_o_10,load_flush_selected[10]);
assign vld_entry[11]           =entry_vld_o_11                               ;
assign wait_state[11]          =entry_req_state_o_11==1                      ;
assign mem_aces_state[11]      =entry_req_state_o_11==2                      ;
assign dev_aces_state[11]      =entry_req_state_o_11==3                      ;
assign cache_miss_state[11]    =entry_req_state_o_11==4                      ;
assign ddr_aces_state[11]      =entry_req_state_o_11==5                      ;
assign ready_state[11]         =entry_req_state_o_11==6                      ;
assign dev_arready_state[11]   =entry_req_state_o_11==7                      ;
rob_id_cmpo #(.DW(5+1)) load_flush_selected_cmpo_11 (lsu_flush_id,entry_inst_id_o_11,load_flush_selected[11]);
assign vld_entry[12]           =entry_vld_o_12                               ;
assign wait_state[12]          =entry_req_state_o_12==1                      ;
assign mem_aces_state[12]      =entry_req_state_o_12==2                      ;
assign dev_aces_state[12]      =entry_req_state_o_12==3                      ;
assign cache_miss_state[12]    =entry_req_state_o_12==4                      ;
assign ddr_aces_state[12]      =entry_req_state_o_12==5                      ;
assign ready_state[12]         =entry_req_state_o_12==6                      ;
assign dev_arready_state[12]   =entry_req_state_o_12==7                      ;
rob_id_cmpo #(.DW(5+1)) load_flush_selected_cmpo_12 (lsu_flush_id,entry_inst_id_o_12,load_flush_selected[12]);
assign vld_entry[13]           =entry_vld_o_13                               ;
assign wait_state[13]          =entry_req_state_o_13==1                      ;
assign mem_aces_state[13]      =entry_req_state_o_13==2                      ;
assign dev_aces_state[13]      =entry_req_state_o_13==3                      ;
assign cache_miss_state[13]    =entry_req_state_o_13==4                      ;
assign ddr_aces_state[13]      =entry_req_state_o_13==5                      ;
assign ready_state[13]         =entry_req_state_o_13==6                      ;
assign dev_arready_state[13]   =entry_req_state_o_13==7                      ;
rob_id_cmpo #(.DW(5+1)) load_flush_selected_cmpo_13 (lsu_flush_id,entry_inst_id_o_13,load_flush_selected[13]);
assign vld_entry[14]           =entry_vld_o_14                               ;
assign wait_state[14]          =entry_req_state_o_14==1                      ;
assign mem_aces_state[14]      =entry_req_state_o_14==2                      ;
assign dev_aces_state[14]      =entry_req_state_o_14==3                      ;
assign cache_miss_state[14]    =entry_req_state_o_14==4                      ;
assign ddr_aces_state[14]      =entry_req_state_o_14==5                      ;
assign ready_state[14]         =entry_req_state_o_14==6                      ;
assign dev_arready_state[14]   =entry_req_state_o_14==7                      ;
rob_id_cmpo #(.DW(5+1)) load_flush_selected_cmpo_14 (lsu_flush_id,entry_inst_id_o_14,load_flush_selected[14]);
assign vld_entry[15]           =entry_vld_o_15                               ;
assign wait_state[15]          =entry_req_state_o_15==1                      ;
assign mem_aces_state[15]      =entry_req_state_o_15==2                      ;
assign dev_aces_state[15]      =entry_req_state_o_15==3                      ;
assign cache_miss_state[15]    =entry_req_state_o_15==4                      ;
assign ddr_aces_state[15]      =entry_req_state_o_15==5                      ;
assign ready_state[15]         =entry_req_state_o_15==6                      ;
assign dev_arready_state[15]   =entry_req_state_o_15==7                      ;
rob_id_cmpo #(.DW(5+1)) load_flush_selected_cmpo_15 (lsu_flush_id,entry_inst_id_o_15,load_flush_selected[15]);

//dmem read
assign dmem_load_addr =
({32{mem_selector_out==0}} & entry_addr_o_0 )|
({32{mem_selector_out==1}} & entry_addr_o_1 )|
({32{mem_selector_out==2}} & entry_addr_o_2 )|
({32{mem_selector_out==3}} & entry_addr_o_3 )|
({32{mem_selector_out==4}} & entry_addr_o_4 )|
({32{mem_selector_out==5}} & entry_addr_o_5 )|
({32{mem_selector_out==6}} & entry_addr_o_6 )|
({32{mem_selector_out==7}} & entry_addr_o_7 )|
({32{mem_selector_out==8}} & entry_addr_o_8 )|
({32{mem_selector_out==9}} & entry_addr_o_9 )|
({32{mem_selector_out==10}} & entry_addr_o_10 )|
({32{mem_selector_out==11}} & entry_addr_o_11 )|
({32{mem_selector_out==12}} & entry_addr_o_12 )|
({32{mem_selector_out==13}} & entry_addr_o_13 )|
({32{mem_selector_out==14}} & entry_addr_o_14 )|
({32{mem_selector_out==15}} & entry_addr_o_15);
assign dmem_load_req_tid =
({32{mem_selector_out==0}} & entry_inst_id_o_0 )|
({32{mem_selector_out==1}} & entry_inst_id_o_1 )|
({32{mem_selector_out==2}} & entry_inst_id_o_2 )|
({32{mem_selector_out==3}} & entry_inst_id_o_3 )|
({32{mem_selector_out==4}} & entry_inst_id_o_4 )|
({32{mem_selector_out==5}} & entry_inst_id_o_5 )|
({32{mem_selector_out==6}} & entry_inst_id_o_6 )|
({32{mem_selector_out==7}} & entry_inst_id_o_7 )|
({32{mem_selector_out==8}} & entry_inst_id_o_8 )|
({32{mem_selector_out==9}} & entry_inst_id_o_9 )|
({32{mem_selector_out==10}} & entry_inst_id_o_10 )|
({32{mem_selector_out==11}} & entry_inst_id_o_11 )|
({32{mem_selector_out==12}} & entry_inst_id_o_12 )|
({32{mem_selector_out==13}} & entry_inst_id_o_13 )|
({32{mem_selector_out==14}} & entry_inst_id_o_14 )|
({32{mem_selector_out==15}} & entry_inst_id_o_15);
assign dmem_load_info =
({32{mem_selector_out==0}} & entry_req_info_o_0 )|
({32{mem_selector_out==1}} & entry_req_info_o_1 )|
({32{mem_selector_out==2}} & entry_req_info_o_2 )|
({32{mem_selector_out==3}} & entry_req_info_o_3 )|
({32{mem_selector_out==4}} & entry_req_info_o_4 )|
({32{mem_selector_out==5}} & entry_req_info_o_5 )|
({32{mem_selector_out==6}} & entry_req_info_o_6 )|
({32{mem_selector_out==7}} & entry_req_info_o_7 )|
({32{mem_selector_out==8}} & entry_req_info_o_8 )|
({32{mem_selector_out==9}} & entry_req_info_o_9 )|
({32{mem_selector_out==10}} & entry_req_info_o_10 )|
({32{mem_selector_out==11}} & entry_req_info_o_11 )|
({32{mem_selector_out==12}} & entry_req_info_o_12 )|
({32{mem_selector_out==13}} & entry_req_info_o_13 )|
({32{mem_selector_out==14}} & entry_req_info_o_14 )|
({32{mem_selector_out==15}} & entry_req_info_o_15);



assign ddr_load_addr =
({32{ddr_selector_out==0}} & entry_addr_o_0 )|
({32{ddr_selector_out==1}} & entry_addr_o_1 )|
({32{ddr_selector_out==2}} & entry_addr_o_2 )|
({32{ddr_selector_out==3}} & entry_addr_o_3 )|
({32{ddr_selector_out==4}} & entry_addr_o_4 )|
({32{ddr_selector_out==5}} & entry_addr_o_5 )|
({32{ddr_selector_out==6}} & entry_addr_o_6 )|
({32{ddr_selector_out==7}} & entry_addr_o_7 )|
({32{ddr_selector_out==8}} & entry_addr_o_8 )|
({32{ddr_selector_out==9}} & entry_addr_o_9 )|
({32{ddr_selector_out==10}} & entry_addr_o_10 )|
({32{ddr_selector_out==11}} & entry_addr_o_11 )|
({32{ddr_selector_out==12}} & entry_addr_o_12 )|
({32{ddr_selector_out==13}} & entry_addr_o_13 )|
({32{ddr_selector_out==14}} & entry_addr_o_14 )|
({32{ddr_selector_out==15}} & entry_addr_o_15);
assign ddr_load_req_tid =
({32{ddr_selector_out==0}} & entry_inst_id_o_0 )|
({32{ddr_selector_out==1}} & entry_inst_id_o_1 )|
({32{ddr_selector_out==2}} & entry_inst_id_o_2 )|
({32{ddr_selector_out==3}} & entry_inst_id_o_3 )|
({32{ddr_selector_out==4}} & entry_inst_id_o_4 )|
({32{ddr_selector_out==5}} & entry_inst_id_o_5 )|
({32{ddr_selector_out==6}} & entry_inst_id_o_6 )|
({32{ddr_selector_out==7}} & entry_inst_id_o_7 )|
({32{ddr_selector_out==8}} & entry_inst_id_o_8 )|
({32{ddr_selector_out==9}} & entry_inst_id_o_9 )|
({32{ddr_selector_out==10}} & entry_inst_id_o_10 )|
({32{ddr_selector_out==11}} & entry_inst_id_o_11 )|
({32{ddr_selector_out==12}} & entry_inst_id_o_12 )|
({32{ddr_selector_out==13}} & entry_inst_id_o_13 )|
({32{ddr_selector_out==14}} & entry_inst_id_o_14 )|
({32{ddr_selector_out==15}} & entry_inst_id_o_15);



assign dev_load_addr =
({32{dev_selector_out==0}} & entry_addr_o_0 )|
({32{dev_selector_out==1}} & entry_addr_o_1 )|
({32{dev_selector_out==2}} & entry_addr_o_2 )|
({32{dev_selector_out==3}} & entry_addr_o_3 )|
({32{dev_selector_out==4}} & entry_addr_o_4 )|
({32{dev_selector_out==5}} & entry_addr_o_5 )|
({32{dev_selector_out==6}} & entry_addr_o_6 )|
({32{dev_selector_out==7}} & entry_addr_o_7 )|
({32{dev_selector_out==8}} & entry_addr_o_8 )|
({32{dev_selector_out==9}} & entry_addr_o_9 )|
({32{dev_selector_out==10}} & entry_addr_o_10 )|
({32{dev_selector_out==11}} & entry_addr_o_11 )|
({32{dev_selector_out==12}} & entry_addr_o_12 )|
({32{dev_selector_out==13}} & entry_addr_o_13 )|
({32{dev_selector_out==14}} & entry_addr_o_14 )|
({32{dev_selector_out==15}} & entry_addr_o_15);

assign dev_load_tid =
({32{dev_selector_out==0}} & entry_inst_id_o_0 )|
({32{dev_selector_out==1}} & entry_inst_id_o_1 )|
({32{dev_selector_out==2}} & entry_inst_id_o_2 )|
({32{dev_selector_out==3}} & entry_inst_id_o_3 )|
({32{dev_selector_out==4}} & entry_inst_id_o_4 )|
({32{dev_selector_out==5}} & entry_inst_id_o_5 )|
({32{dev_selector_out==6}} & entry_inst_id_o_6 )|
({32{dev_selector_out==7}} & entry_inst_id_o_7 )|
({32{dev_selector_out==8}} & entry_inst_id_o_8 )|
({32{dev_selector_out==9}} & entry_inst_id_o_9 )|
({32{dev_selector_out==10}} & entry_inst_id_o_10 )|
({32{dev_selector_out==11}} & entry_inst_id_o_11 )|
({32{dev_selector_out==12}} & entry_inst_id_o_12 )|
({32{dev_selector_out==13}} & entry_inst_id_o_13 )|
({32{dev_selector_out==14}} & entry_inst_id_o_14 )|
({32{dev_selector_out==15}} & entry_inst_id_o_15);
//inst entry
frv_load_entry inst_frv_load_entry_0                       
    (                                                       
        .clk                    (clk)                      ,
        .pd_rst                 (pd_rst)                   ,
        .rst_n                  (rst_n)                    ,
        .entry_in_selected      (entry_in_selected_0)     ,
        .entry_mem_selected     (entry_mem_selected_0)    ,
        .entry_dev_selected     (entry_dev_selected_0)    ,
        .entry_resp_selected    (entry_resp_selected_0)   ,
        .entry_ddr_selected     (entry_ddr_selected_0)    ,
        .entry_RAW_selected     (entry_RAW_selected_0)    ,
        .entry_flush_selected   (entry_flush_selected_0)  ,
        .entry_cache_miss       (entry_cache_miss_0)      ,
        .entry_cache_hit        (entry_cache_hit_0)       ,
        .entry_ddr_ack          (entry_ddr_ack_0)         ,
        .entry_dev_arready      (entry_dev_arready_0)     ,
        .entry_dev_rvalid       (entry_dev_rvalid_0)      ,
        .entry_dev_rresp        (entry_dev_rresp_0)       ,
        .load_entry_addr             (entry_addr_0)            ,
        .load_entry_inst_id          (entry_inst_id_0)         ,
        .load_entry_req_type         (entry_req_type_0)        ,
        .load_entry_resp_data        (entry_resp_data_0)       ,
        .load_entry_req_info         (entry_req_info_0)        ,
        .load_entry_addr_o           (entry_addr_o_0)          ,
        .load_entry_inst_id_o        (entry_inst_id_o_0)       ,
        .load_entry_vld_o            (entry_vld_o_0)           ,
        .load_entry_req_state_o      (entry_req_state_o_0)     ,
        .load_entry_req_type_o       (entry_req_type_o_0)      ,
        .load_entry_resp_data_o      (entry_resp_data_o_0)     ,
        .load_entry_req_info_o       (entry_req_info_o_0)      
    );
                                                    
frv_load_entry inst_frv_load_entry_1                       
    (                                                       
        .clk                    (clk)                      ,
        .pd_rst                 (pd_rst)                   ,
        .rst_n                  (rst_n)                    ,
        .entry_in_selected      (entry_in_selected_1)     ,
        .entry_mem_selected     (entry_mem_selected_1)    ,
        .entry_dev_selected     (entry_dev_selected_1)    ,
        .entry_resp_selected    (entry_resp_selected_1)   ,
        .entry_ddr_selected     (entry_ddr_selected_1)    ,
        .entry_RAW_selected     (entry_RAW_selected_1)    ,
        .entry_flush_selected   (entry_flush_selected_1)  ,
        .entry_cache_miss       (entry_cache_miss_1)      ,
        .entry_cache_hit        (entry_cache_hit_1)       ,
        .entry_ddr_ack          (entry_ddr_ack_1)         ,
        .entry_dev_arready      (entry_dev_arready_1)     ,
        .entry_dev_rvalid       (entry_dev_rvalid_1)      ,
        .entry_dev_rresp        (entry_dev_rresp_1)       ,
        .load_entry_addr             (entry_addr_1)            ,
        .load_entry_inst_id          (entry_inst_id_1)         ,
        .load_entry_req_type         (entry_req_type_1)        ,
        .load_entry_resp_data        (entry_resp_data_1)       ,
        .load_entry_req_info         (entry_req_info_1)        ,
        .load_entry_addr_o           (entry_addr_o_1)          ,
        .load_entry_inst_id_o        (entry_inst_id_o_1)       ,
        .load_entry_vld_o            (entry_vld_o_1)           ,
        .load_entry_req_state_o      (entry_req_state_o_1)     ,
        .load_entry_req_type_o       (entry_req_type_o_1)      ,
        .load_entry_resp_data_o      (entry_resp_data_o_1)     ,
        .load_entry_req_info_o       (entry_req_info_o_1)      
    );
                                                    
frv_load_entry inst_frv_load_entry_2                       
    (                                                       
        .clk                    (clk)                      ,
        .pd_rst                 (pd_rst)                   ,
        .rst_n                  (rst_n)                    ,
        .entry_in_selected      (entry_in_selected_2)     ,
        .entry_mem_selected     (entry_mem_selected_2)    ,
        .entry_dev_selected     (entry_dev_selected_2)    ,
        .entry_resp_selected    (entry_resp_selected_2)   ,
        .entry_ddr_selected     (entry_ddr_selected_2)    ,
        .entry_RAW_selected     (entry_RAW_selected_2)    ,
        .entry_flush_selected   (entry_flush_selected_2)  ,
        .entry_cache_miss       (entry_cache_miss_2)      ,
        .entry_cache_hit        (entry_cache_hit_2)       ,
        .entry_ddr_ack          (entry_ddr_ack_2)         ,
        .entry_dev_arready      (entry_dev_arready_2)     ,
        .entry_dev_rvalid       (entry_dev_rvalid_2)      ,
        .entry_dev_rresp        (entry_dev_rresp_2)       ,
        .load_entry_addr             (entry_addr_2)            ,
        .load_entry_inst_id          (entry_inst_id_2)         ,
        .load_entry_req_type         (entry_req_type_2)        ,
        .load_entry_resp_data        (entry_resp_data_2)       ,
        .load_entry_req_info         (entry_req_info_2)        ,
        .load_entry_addr_o           (entry_addr_o_2)          ,
        .load_entry_inst_id_o        (entry_inst_id_o_2)       ,
        .load_entry_vld_o            (entry_vld_o_2)           ,
        .load_entry_req_state_o      (entry_req_state_o_2)     ,
        .load_entry_req_type_o       (entry_req_type_o_2)      ,
        .load_entry_resp_data_o      (entry_resp_data_o_2)     ,
        .load_entry_req_info_o       (entry_req_info_o_2)      
    );
                                                    
frv_load_entry inst_frv_load_entry_3                       
    (                                                       
        .clk                    (clk)                      ,
        .pd_rst                 (pd_rst)                   ,
        .rst_n                  (rst_n)                    ,
        .entry_in_selected      (entry_in_selected_3)     ,
        .entry_mem_selected     (entry_mem_selected_3)    ,
        .entry_dev_selected     (entry_dev_selected_3)    ,
        .entry_resp_selected    (entry_resp_selected_3)   ,
        .entry_ddr_selected     (entry_ddr_selected_3)    ,
        .entry_RAW_selected     (entry_RAW_selected_3)    ,
        .entry_flush_selected   (entry_flush_selected_3)  ,
        .entry_cache_miss       (entry_cache_miss_3)      ,
        .entry_cache_hit        (entry_cache_hit_3)       ,
        .entry_ddr_ack          (entry_ddr_ack_3)         ,
        .entry_dev_arready      (entry_dev_arready_3)     ,
        .entry_dev_rvalid       (entry_dev_rvalid_3)      ,
        .entry_dev_rresp        (entry_dev_rresp_3)       ,
        .load_entry_addr             (entry_addr_3)            ,
        .load_entry_inst_id          (entry_inst_id_3)         ,
        .load_entry_req_type         (entry_req_type_3)        ,
        .load_entry_resp_data        (entry_resp_data_3)       ,
        .load_entry_req_info         (entry_req_info_3)        ,
        .load_entry_addr_o           (entry_addr_o_3)          ,
        .load_entry_inst_id_o        (entry_inst_id_o_3)       ,
        .load_entry_vld_o            (entry_vld_o_3)           ,
        .load_entry_req_state_o      (entry_req_state_o_3)     ,
        .load_entry_req_type_o       (entry_req_type_o_3)      ,
        .load_entry_resp_data_o      (entry_resp_data_o_3)     ,
        .load_entry_req_info_o       (entry_req_info_o_3)      
    );
                                                    
frv_load_entry inst_frv_load_entry_4                       
    (                                                       
        .clk                    (clk)                      ,
        .pd_rst                 (pd_rst)                   ,
        .rst_n                  (rst_n)                    ,
        .entry_in_selected      (entry_in_selected_4)     ,
        .entry_mem_selected     (entry_mem_selected_4)    ,
        .entry_dev_selected     (entry_dev_selected_4)    ,
        .entry_resp_selected    (entry_resp_selected_4)   ,
        .entry_ddr_selected     (entry_ddr_selected_4)    ,
        .entry_RAW_selected     (entry_RAW_selected_4)    ,
        .entry_flush_selected   (entry_flush_selected_4)  ,
        .entry_cache_miss       (entry_cache_miss_4)      ,
        .entry_cache_hit        (entry_cache_hit_4)       ,
        .entry_ddr_ack          (entry_ddr_ack_4)         ,
        .entry_dev_arready      (entry_dev_arready_4)     ,
        .entry_dev_rvalid       (entry_dev_rvalid_4)      ,
        .entry_dev_rresp        (entry_dev_rresp_4)       ,
        .load_entry_addr             (entry_addr_4)            ,
        .load_entry_inst_id          (entry_inst_id_4)         ,
        .load_entry_req_type         (entry_req_type_4)        ,
        .load_entry_resp_data        (entry_resp_data_4)       ,
        .load_entry_req_info         (entry_req_info_4)        ,
        .load_entry_addr_o           (entry_addr_o_4)          ,
        .load_entry_inst_id_o        (entry_inst_id_o_4)       ,
        .load_entry_vld_o            (entry_vld_o_4)           ,
        .load_entry_req_state_o      (entry_req_state_o_4)     ,
        .load_entry_req_type_o       (entry_req_type_o_4)      ,
        .load_entry_resp_data_o      (entry_resp_data_o_4)     ,
        .load_entry_req_info_o       (entry_req_info_o_4)      
    );
                                                    
frv_load_entry inst_frv_load_entry_5                       
    (                                                       
        .clk                    (clk)                      ,
        .pd_rst                 (pd_rst)                   ,
        .rst_n                  (rst_n)                    ,
        .entry_in_selected      (entry_in_selected_5)     ,
        .entry_mem_selected     (entry_mem_selected_5)    ,
        .entry_dev_selected     (entry_dev_selected_5)    ,
        .entry_resp_selected    (entry_resp_selected_5)   ,
        .entry_ddr_selected     (entry_ddr_selected_5)    ,
        .entry_RAW_selected     (entry_RAW_selected_5)    ,
        .entry_flush_selected   (entry_flush_selected_5)  ,
        .entry_cache_miss       (entry_cache_miss_5)      ,
        .entry_cache_hit        (entry_cache_hit_5)       ,
        .entry_ddr_ack          (entry_ddr_ack_5)         ,
        .entry_dev_arready      (entry_dev_arready_5)     ,
        .entry_dev_rvalid       (entry_dev_rvalid_5)      ,
        .entry_dev_rresp        (entry_dev_rresp_5)       ,
        .load_entry_addr             (entry_addr_5)            ,
        .load_entry_inst_id          (entry_inst_id_5)         ,
        .load_entry_req_type         (entry_req_type_5)        ,
        .load_entry_resp_data        (entry_resp_data_5)       ,
        .load_entry_req_info         (entry_req_info_5)        ,
        .load_entry_addr_o           (entry_addr_o_5)          ,
        .load_entry_inst_id_o        (entry_inst_id_o_5)       ,
        .load_entry_vld_o            (entry_vld_o_5)           ,
        .load_entry_req_state_o      (entry_req_state_o_5)     ,
        .load_entry_req_type_o       (entry_req_type_o_5)      ,
        .load_entry_resp_data_o      (entry_resp_data_o_5)     ,
        .load_entry_req_info_o       (entry_req_info_o_5)      
    );
                                                    
frv_load_entry inst_frv_load_entry_6                       
    (                                                       
        .clk                    (clk)                      ,
        .pd_rst                 (pd_rst)                   ,
        .rst_n                  (rst_n)                    ,
        .entry_in_selected      (entry_in_selected_6)     ,
        .entry_mem_selected     (entry_mem_selected_6)    ,
        .entry_dev_selected     (entry_dev_selected_6)    ,
        .entry_resp_selected    (entry_resp_selected_6)   ,
        .entry_ddr_selected     (entry_ddr_selected_6)    ,
        .entry_RAW_selected     (entry_RAW_selected_6)    ,
        .entry_flush_selected   (entry_flush_selected_6)  ,
        .entry_cache_miss       (entry_cache_miss_6)      ,
        .entry_cache_hit        (entry_cache_hit_6)       ,
        .entry_ddr_ack          (entry_ddr_ack_6)         ,
        .entry_dev_arready      (entry_dev_arready_6)     ,
        .entry_dev_rvalid       (entry_dev_rvalid_6)      ,
        .entry_dev_rresp        (entry_dev_rresp_6)       ,
        .load_entry_addr             (entry_addr_6)            ,
        .load_entry_inst_id          (entry_inst_id_6)         ,
        .load_entry_req_type         (entry_req_type_6)        ,
        .load_entry_resp_data        (entry_resp_data_6)       ,
        .load_entry_req_info         (entry_req_info_6)        ,
        .load_entry_addr_o           (entry_addr_o_6)          ,
        .load_entry_inst_id_o        (entry_inst_id_o_6)       ,
        .load_entry_vld_o            (entry_vld_o_6)           ,
        .load_entry_req_state_o      (entry_req_state_o_6)     ,
        .load_entry_req_type_o       (entry_req_type_o_6)      ,
        .load_entry_resp_data_o      (entry_resp_data_o_6)     ,
        .load_entry_req_info_o       (entry_req_info_o_6)      
    );
                                                    
frv_load_entry inst_frv_load_entry_7                       
    (                                                       
        .clk                    (clk)                      ,
        .pd_rst                 (pd_rst)                   ,
        .rst_n                  (rst_n)                    ,
        .entry_in_selected      (entry_in_selected_7)     ,
        .entry_mem_selected     (entry_mem_selected_7)    ,
        .entry_dev_selected     (entry_dev_selected_7)    ,
        .entry_resp_selected    (entry_resp_selected_7)   ,
        .entry_ddr_selected     (entry_ddr_selected_7)    ,
        .entry_RAW_selected     (entry_RAW_selected_7)    ,
        .entry_flush_selected   (entry_flush_selected_7)  ,
        .entry_cache_miss       (entry_cache_miss_7)      ,
        .entry_cache_hit        (entry_cache_hit_7)       ,
        .entry_ddr_ack          (entry_ddr_ack_7)         ,
        .entry_dev_arready      (entry_dev_arready_7)     ,
        .entry_dev_rvalid       (entry_dev_rvalid_7)      ,
        .entry_dev_rresp        (entry_dev_rresp_7)       ,
        .load_entry_addr             (entry_addr_7)            ,
        .load_entry_inst_id          (entry_inst_id_7)         ,
        .load_entry_req_type         (entry_req_type_7)        ,
        .load_entry_resp_data        (entry_resp_data_7)       ,
        .load_entry_req_info         (entry_req_info_7)        ,
        .load_entry_addr_o           (entry_addr_o_7)          ,
        .load_entry_inst_id_o        (entry_inst_id_o_7)       ,
        .load_entry_vld_o            (entry_vld_o_7)           ,
        .load_entry_req_state_o      (entry_req_state_o_7)     ,
        .load_entry_req_type_o       (entry_req_type_o_7)      ,
        .load_entry_resp_data_o      (entry_resp_data_o_7)     ,
        .load_entry_req_info_o       (entry_req_info_o_7)      
    );
                                                    
frv_load_entry inst_frv_load_entry_8                       
    (                                                       
        .clk                    (clk)                      ,
        .pd_rst                 (pd_rst)                   ,
        .rst_n                  (rst_n)                    ,
        .entry_in_selected      (entry_in_selected_8)     ,
        .entry_mem_selected     (entry_mem_selected_8)    ,
        .entry_dev_selected     (entry_dev_selected_8)    ,
        .entry_resp_selected    (entry_resp_selected_8)   ,
        .entry_ddr_selected     (entry_ddr_selected_8)    ,
        .entry_RAW_selected     (entry_RAW_selected_8)    ,
        .entry_flush_selected   (entry_flush_selected_8)  ,
        .entry_cache_miss       (entry_cache_miss_8)      ,
        .entry_cache_hit        (entry_cache_hit_8)       ,
        .entry_ddr_ack          (entry_ddr_ack_8)         ,
        .entry_dev_arready      (entry_dev_arready_8)     ,
        .entry_dev_rvalid       (entry_dev_rvalid_8)      ,
        .entry_dev_rresp        (entry_dev_rresp_8)       ,
        .load_entry_addr             (entry_addr_8)            ,
        .load_entry_inst_id          (entry_inst_id_8)         ,
        .load_entry_req_type         (entry_req_type_8)        ,
        .load_entry_resp_data        (entry_resp_data_8)       ,
        .load_entry_req_info         (entry_req_info_8)        ,
        .load_entry_addr_o           (entry_addr_o_8)          ,
        .load_entry_inst_id_o        (entry_inst_id_o_8)       ,
        .load_entry_vld_o            (entry_vld_o_8)           ,
        .load_entry_req_state_o      (entry_req_state_o_8)     ,
        .load_entry_req_type_o       (entry_req_type_o_8)      ,
        .load_entry_resp_data_o      (entry_resp_data_o_8)     ,
        .load_entry_req_info_o       (entry_req_info_o_8)      
    );
                                                    
frv_load_entry inst_frv_load_entry_9                       
    (                                                       
        .clk                    (clk)                      ,
        .pd_rst                 (pd_rst)                   ,
        .rst_n                  (rst_n)                    ,
        .entry_in_selected      (entry_in_selected_9)     ,
        .entry_mem_selected     (entry_mem_selected_9)    ,
        .entry_dev_selected     (entry_dev_selected_9)    ,
        .entry_resp_selected    (entry_resp_selected_9)   ,
        .entry_ddr_selected     (entry_ddr_selected_9)    ,
        .entry_RAW_selected     (entry_RAW_selected_9)    ,
        .entry_flush_selected   (entry_flush_selected_9)  ,
        .entry_cache_miss       (entry_cache_miss_9)      ,
        .entry_cache_hit        (entry_cache_hit_9)       ,
        .entry_ddr_ack          (entry_ddr_ack_9)         ,
        .entry_dev_arready      (entry_dev_arready_9)     ,
        .entry_dev_rvalid       (entry_dev_rvalid_9)      ,
        .entry_dev_rresp        (entry_dev_rresp_9)       ,
        .load_entry_addr             (entry_addr_9)            ,
        .load_entry_inst_id          (entry_inst_id_9)         ,
        .load_entry_req_type         (entry_req_type_9)        ,
        .load_entry_resp_data        (entry_resp_data_9)       ,
        .load_entry_req_info         (entry_req_info_9)        ,
        .load_entry_addr_o           (entry_addr_o_9)          ,
        .load_entry_inst_id_o        (entry_inst_id_o_9)       ,
        .load_entry_vld_o            (entry_vld_o_9)           ,
        .load_entry_req_state_o      (entry_req_state_o_9)     ,
        .load_entry_req_type_o       (entry_req_type_o_9)      ,
        .load_entry_resp_data_o      (entry_resp_data_o_9)     ,
        .load_entry_req_info_o       (entry_req_info_o_9)      
    );
                                                    
frv_load_entry inst_frv_load_entry_10                       
    (                                                       
        .clk                    (clk)                      ,
        .pd_rst                 (pd_rst)                   ,
        .rst_n                  (rst_n)                    ,
        .entry_in_selected      (entry_in_selected_10)     ,
        .entry_mem_selected     (entry_mem_selected_10)    ,
        .entry_dev_selected     (entry_dev_selected_10)    ,
        .entry_resp_selected    (entry_resp_selected_10)   ,
        .entry_ddr_selected     (entry_ddr_selected_10)    ,
        .entry_RAW_selected     (entry_RAW_selected_10)    ,
        .entry_flush_selected   (entry_flush_selected_10)  ,
        .entry_cache_miss       (entry_cache_miss_10)      ,
        .entry_cache_hit        (entry_cache_hit_10)       ,
        .entry_ddr_ack          (entry_ddr_ack_10)         ,
        .entry_dev_arready      (entry_dev_arready_10)     ,
        .entry_dev_rvalid       (entry_dev_rvalid_10)      ,
        .entry_dev_rresp        (entry_dev_rresp_10)       ,
        .load_entry_addr             (entry_addr_10)            ,
        .load_entry_inst_id          (entry_inst_id_10)         ,
        .load_entry_req_type         (entry_req_type_10)        ,
        .load_entry_resp_data        (entry_resp_data_10)       ,
        .load_entry_req_info         (entry_req_info_10)        ,
        .load_entry_addr_o           (entry_addr_o_10)          ,
        .load_entry_inst_id_o        (entry_inst_id_o_10)       ,
        .load_entry_vld_o            (entry_vld_o_10)           ,
        .load_entry_req_state_o      (entry_req_state_o_10)     ,
        .load_entry_req_type_o       (entry_req_type_o_10)      ,
        .load_entry_resp_data_o      (entry_resp_data_o_10)     ,
        .load_entry_req_info_o       (entry_req_info_o_10)      
    );
                                                    
frv_load_entry inst_frv_load_entry_11                       
    (                                                       
        .clk                    (clk)                      ,
        .pd_rst                 (pd_rst)                   ,
        .rst_n                  (rst_n)                    ,
        .entry_in_selected      (entry_in_selected_11)     ,
        .entry_mem_selected     (entry_mem_selected_11)    ,
        .entry_dev_selected     (entry_dev_selected_11)    ,
        .entry_resp_selected    (entry_resp_selected_11)   ,
        .entry_ddr_selected     (entry_ddr_selected_11)    ,
        .entry_RAW_selected     (entry_RAW_selected_11)    ,
        .entry_flush_selected   (entry_flush_selected_11)  ,
        .entry_cache_miss       (entry_cache_miss_11)      ,
        .entry_cache_hit        (entry_cache_hit_11)       ,
        .entry_ddr_ack          (entry_ddr_ack_11)         ,
        .entry_dev_arready      (entry_dev_arready_11)     ,
        .entry_dev_rvalid       (entry_dev_rvalid_11)      ,
        .entry_dev_rresp        (entry_dev_rresp_11)       ,
        .load_entry_addr             (entry_addr_11)            ,
        .load_entry_inst_id          (entry_inst_id_11)         ,
        .load_entry_req_type         (entry_req_type_11)        ,
        .load_entry_resp_data        (entry_resp_data_11)       ,
        .load_entry_req_info         (entry_req_info_11)        ,
        .load_entry_addr_o           (entry_addr_o_11)          ,
        .load_entry_inst_id_o        (entry_inst_id_o_11)       ,
        .load_entry_vld_o            (entry_vld_o_11)           ,
        .load_entry_req_state_o      (entry_req_state_o_11)     ,
        .load_entry_req_type_o       (entry_req_type_o_11)      ,
        .load_entry_resp_data_o      (entry_resp_data_o_11)     ,
        .load_entry_req_info_o       (entry_req_info_o_11)      
    );
                                                    
frv_load_entry inst_frv_load_entry_12                       
    (                                                       
        .clk                    (clk)                      ,
        .pd_rst                 (pd_rst)                   ,
        .rst_n                  (rst_n)                    ,
        .entry_in_selected      (entry_in_selected_12)     ,
        .entry_mem_selected     (entry_mem_selected_12)    ,
        .entry_dev_selected     (entry_dev_selected_12)    ,
        .entry_resp_selected    (entry_resp_selected_12)   ,
        .entry_ddr_selected     (entry_ddr_selected_12)    ,
        .entry_RAW_selected     (entry_RAW_selected_12)    ,
        .entry_flush_selected   (entry_flush_selected_12)  ,
        .entry_cache_miss       (entry_cache_miss_12)      ,
        .entry_cache_hit        (entry_cache_hit_12)       ,
        .entry_ddr_ack          (entry_ddr_ack_12)         ,
        .entry_dev_arready      (entry_dev_arready_12)     ,
        .entry_dev_rvalid       (entry_dev_rvalid_12)      ,
        .entry_dev_rresp        (entry_dev_rresp_12)       ,
        .load_entry_addr             (entry_addr_12)            ,
        .load_entry_inst_id          (entry_inst_id_12)         ,
        .load_entry_req_type         (entry_req_type_12)        ,
        .load_entry_resp_data        (entry_resp_data_12)       ,
        .load_entry_req_info         (entry_req_info_12)        ,
        .load_entry_addr_o           (entry_addr_o_12)          ,
        .load_entry_inst_id_o        (entry_inst_id_o_12)       ,
        .load_entry_vld_o            (entry_vld_o_12)           ,
        .load_entry_req_state_o      (entry_req_state_o_12)     ,
        .load_entry_req_type_o       (entry_req_type_o_12)      ,
        .load_entry_resp_data_o      (entry_resp_data_o_12)     ,
        .load_entry_req_info_o       (entry_req_info_o_12)      
    );
                                                    
frv_load_entry inst_frv_load_entry_13                       
    (                                                       
        .clk                    (clk)                      ,
        .pd_rst                 (pd_rst)                   ,
        .rst_n                  (rst_n)                    ,
        .entry_in_selected      (entry_in_selected_13)     ,
        .entry_mem_selected     (entry_mem_selected_13)    ,
        .entry_dev_selected     (entry_dev_selected_13)    ,
        .entry_resp_selected    (entry_resp_selected_13)   ,
        .entry_ddr_selected     (entry_ddr_selected_13)    ,
        .entry_RAW_selected     (entry_RAW_selected_13)    ,
        .entry_flush_selected   (entry_flush_selected_13)  ,
        .entry_cache_miss       (entry_cache_miss_13)      ,
        .entry_cache_hit        (entry_cache_hit_13)       ,
        .entry_ddr_ack          (entry_ddr_ack_13)         ,
        .entry_dev_arready      (entry_dev_arready_13)     ,
        .entry_dev_rvalid       (entry_dev_rvalid_13)      ,
        .entry_dev_rresp        (entry_dev_rresp_13)       ,
        .load_entry_addr             (entry_addr_13)            ,
        .load_entry_inst_id          (entry_inst_id_13)         ,
        .load_entry_req_type         (entry_req_type_13)        ,
        .load_entry_resp_data        (entry_resp_data_13)       ,
        .load_entry_req_info         (entry_req_info_13)        ,
        .load_entry_addr_o           (entry_addr_o_13)          ,
        .load_entry_inst_id_o        (entry_inst_id_o_13)       ,
        .load_entry_vld_o            (entry_vld_o_13)           ,
        .load_entry_req_state_o      (entry_req_state_o_13)     ,
        .load_entry_req_type_o       (entry_req_type_o_13)      ,
        .load_entry_resp_data_o      (entry_resp_data_o_13)     ,
        .load_entry_req_info_o       (entry_req_info_o_13)      
    );
                                                    
frv_load_entry inst_frv_load_entry_14                       
    (                                                       
        .clk                    (clk)                      ,
        .pd_rst                 (pd_rst)                   ,
        .rst_n                  (rst_n)                    ,
        .entry_in_selected      (entry_in_selected_14)     ,
        .entry_mem_selected     (entry_mem_selected_14)    ,
        .entry_dev_selected     (entry_dev_selected_14)    ,
        .entry_resp_selected    (entry_resp_selected_14)   ,
        .entry_ddr_selected     (entry_ddr_selected_14)    ,
        .entry_RAW_selected     (entry_RAW_selected_14)    ,
        .entry_flush_selected   (entry_flush_selected_14)  ,
        .entry_cache_miss       (entry_cache_miss_14)      ,
        .entry_cache_hit        (entry_cache_hit_14)       ,
        .entry_ddr_ack          (entry_ddr_ack_14)         ,
        .entry_dev_arready      (entry_dev_arready_14)     ,
        .entry_dev_rvalid       (entry_dev_rvalid_14)      ,
        .entry_dev_rresp        (entry_dev_rresp_14)       ,
        .load_entry_addr             (entry_addr_14)            ,
        .load_entry_inst_id          (entry_inst_id_14)         ,
        .load_entry_req_type         (entry_req_type_14)        ,
        .load_entry_resp_data        (entry_resp_data_14)       ,
        .load_entry_req_info         (entry_req_info_14)        ,
        .load_entry_addr_o           (entry_addr_o_14)          ,
        .load_entry_inst_id_o        (entry_inst_id_o_14)       ,
        .load_entry_vld_o            (entry_vld_o_14)           ,
        .load_entry_req_state_o      (entry_req_state_o_14)     ,
        .load_entry_req_type_o       (entry_req_type_o_14)      ,
        .load_entry_resp_data_o      (entry_resp_data_o_14)     ,
        .load_entry_req_info_o       (entry_req_info_o_14)      
    );
                                                    
frv_load_entry inst_frv_load_entry_15                       
    (                                                       
        .clk                    (clk)                      ,
        .pd_rst                 (pd_rst)                   ,
        .rst_n                  (rst_n)                    ,
        .entry_in_selected      (entry_in_selected_15)     ,
        .entry_mem_selected     (entry_mem_selected_15)    ,
        .entry_dev_selected     (entry_dev_selected_15)    ,
        .entry_resp_selected    (entry_resp_selected_15)   ,
        .entry_ddr_selected     (entry_ddr_selected_15)    ,
        .entry_RAW_selected     (entry_RAW_selected_15)    ,
        .entry_flush_selected   (entry_flush_selected_15)  ,
        .entry_cache_miss       (entry_cache_miss_15)      ,
        .entry_cache_hit        (entry_cache_hit_15)       ,
        .entry_ddr_ack          (entry_ddr_ack_15)         ,
        .entry_dev_arready      (entry_dev_arready_15)     ,
        .entry_dev_rvalid       (entry_dev_rvalid_15)      ,
        .entry_dev_rresp        (entry_dev_rresp_15)       ,
        .load_entry_addr             (entry_addr_15)            ,
        .load_entry_inst_id          (entry_inst_id_15)         ,
        .load_entry_req_type         (entry_req_type_15)        ,
        .load_entry_resp_data        (entry_resp_data_15)       ,
        .load_entry_req_info         (entry_req_info_15)        ,
        .load_entry_addr_o           (entry_addr_o_15)          ,
        .load_entry_inst_id_o        (entry_inst_id_o_15)       ,
        .load_entry_vld_o            (entry_vld_o_15)           ,
        .load_entry_req_state_o      (entry_req_state_o_15)     ,
        .load_entry_req_type_o       (entry_req_type_o_15)      ,
        .load_entry_resp_data_o      (entry_resp_data_o_15)     ,
        .load_entry_req_info_o       (entry_req_info_o_15)      
    );
                                                    


endmodule




